The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Nov. 09, 2023
Applicant:

Hilight Semiconductor Limited, Southampton, GB;

Inventors:

Rudolf Van Ettinger, Southampton, GB;

Albrecht Johannes Schiff, Southampton, GB;

Richard Horn, Southampton, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/60 (2013.01); H03F 3/45 (2006.01); H04B 10/25 (2013.01);
U.S. Cl.
CPC ...
H04B 10/60 (2013.01); H03F 3/45475 (2013.01); H04B 10/25 (2013.01); H03F 2203/45116 (2013.01); H03F 2203/45511 (2013.01); H03F 2203/45512 (2013.01); H03F 2203/45528 (2013.01);
Abstract

Assemblies of electronic components for reception of data using optical fibre and methods for providing same. Assemblies comprise a photodiode; an amplifier coupled to the photodiode; at least one feedback resistor coupled between the input and output of the amplifier; an arrangement of at least two MOS transistors of same channel polarity and configured in parallel with the feedback resistor(s); a system for sensing received input signal level and applying a bias voltage to gates of the MOS transistors, the bias voltage varied according to the received input signal level to control a resistance apparent through the arrangement of MOS transistors; at least one capacitor configured to couple signals from the amplifier output to a gate of at least one of the MOS transistors; and at least one bias resistor configured to couple the bias voltage to a gate of at least one of the MOS transistors.


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