The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Aug. 14, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Shahin Mehdizad Taleie, San Diego, CA (US);

Dongwon Seo, San Diego, CA (US);

Bhushan Shanti Asuri, San Diego, CA (US);

Ibrahim Ramez Chamas, Carlsbad, CA (US);

Huan Wang, Irvine, CA (US);

Zhiheng Wang, San Diego, CA (US);

Reza Rodd, San Diego, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/01 (2013.01); H03K 19/20 (2013.01); H03K 2005/00019 (2013.01);
Abstract

Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.


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