The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2026
Filed:
Sep. 08, 2023
Applicant:
Schott Glass Technologies (Suzhou) Co. Ltd., Suzhou, CN;
Inventors:
Alex Wang, Suzhou, CN;
Helen Fang, Suzhou, CN;
Zhengyang Lu, Suzhou, CN;
Clemens Ottermann, Hattersheim, DE;
Stefan Weidlich, Suzhou, CN;
Assignee:
SCHOTT Glass Technologies (Suzhou) Co. Ltd., Suzhou, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 9/08 (2006.01); B24B 37/04 (2012.01); C03B 25/00 (2006.01); C03C 3/062 (2006.01); C03C 3/064 (2006.01); C03C 3/066 (2006.01); C03C 3/068 (2006.01); C03C 3/12 (2006.01); C03C 3/14 (2006.01); C03C 3/15 (2006.01); C03C 3/155 (2006.01); C03C 3/16 (2006.01); C03C 3/19 (2006.01); C03C 3/21 (2006.01); C03C 27/06 (2006.01);
U.S. Cl.
CPC ...
B24B 9/08 (2013.01); B24B 37/042 (2013.01); C03B 25/00 (2013.01); C03C 3/062 (2013.01); C03C 3/064 (2013.01); C03C 3/066 (2013.01); C03C 3/068 (2013.01); C03C 3/127 (2013.01); C03C 3/14 (2013.01); C03C 3/15 (2013.01); C03C 3/155 (2013.01); C03C 3/16 (2013.01); C03C 3/19 (2013.01); C03C 3/21 (2013.01); C03C 27/06 (2013.01);
Abstract
A method for manufacturing a glass wafer for augmented reality applications includes the steps of: providing the raw wafer; edge-grinding of the raw wafer; lapping the raw wafer; rough polishing the raw wafer; fine polishing the raw wafer to obtain an intermediate wafer; gluing the intermediate wafer on a flat carrier; performing single-side polishing of a first main side of the intermediate wafer; and performing single-side polishing of a second main side of the intermediate wafer.