The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jul. 21, 2020
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Tadatsugu Yamamoto, Fukuoka, JP;

Ryoji Murai, Fukuoka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 40/47 (2026.01); H10W 40/25 (2026.01); H10W 70/40 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 74/10 (2026.01); H10W 72/50 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 40/47 (2026.01); H10W 40/255 (2026.01); H10W 70/421 (2026.01); H10W 72/952 (2026.01); H10W 74/114 (2026.01); H10W 72/07354 (2026.01); H10W 72/075 (2026.01); H10W 72/347 (2026.01); H10W 72/5524 (2026.01); H10W 72/851 (2026.01); H10W 72/865 (2026.01); H10W 72/884 (2026.01); H10W 74/111 (2026.01); H10W 90/736 (2026.01); H10W 90/755 (2026.01);
Abstract

Heat from a semiconductor device is effectively dissipated while the height of the semiconductor device is kept low. A semiconductor device includes a cooler configured to cool a semiconductor module. The semiconductor module includes: a metal block, a semiconductor element, a terminal connected to the semiconductor element, and a resin covering a part of the terminal, the metal block, and the semiconductor element. The cooler includes: a metal base including the semiconductor module in a plan view while being in contact with a lower surface of the semiconductor module, and a cooling pipe disposed on an upper surface of the metal base and configured to cool the semiconductor module. The cooling pipe at least partially surrounds the semiconductor module in a plan view.


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