The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Feb. 14, 2023
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Christian Rivero, Rousset, FR;

Pascal Fornara, Pourrieres, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/035 (2026.01); H10W 20/034 (2026.01); H10W 20/049 (2026.01); H10W 20/056 (2026.01); H10W 20/42 (2026.01); H10W 20/425 (2026.01);
Abstract

A method of manufacturing a contact on a semiconductor region includes a step of forming a stack of layers on lateral walls and at a bottom of an orifice (aligned with the semiconductor region) crossing a dielectric region along a longitudinal direction. The step of forming step is carried out from a first surface of the dielectric region and includes forming a polysilicon layer and a layer of a first metal in contact with the polysilicon layer. The first metal is preferably a metal selected from the group of transition metals and is well suited to forming with the polysilicon layer a metal silicide. The method further includes a step of performing thermal anneal causing a reaction between the first metal and the polysilicon layer to produce a layer of metal silicide. At least a portion of that layer of metal silicide extends in the longitudinal direction of the orifice.


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