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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12684948 B1

PDFFull Text
Date of Patent:
Jul. 14, 2026

Filed:

Nov. 20, 2020

Display panel, manufacturing method thereof, and display apparatus

Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yao Huang, Beijing, CN;

Yue Long, Beijing, CN;

Weiyun Huang, Beijing, CN;

Assignees:

Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu, CN;

BOE Technology Group Co., Ltd., Beijing, CN;

Attorney:

IPro, PLLC

Primary Examiner:

Michelle Mandala

Int. Cl.
CPC ...
H10K 59/121 (2023.01); H10K 59/12 (2023.01); H10K 59/122 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 71/20 (2023.01); H10K 71/60 (2023.01); H10K 59/80 (2023.01);
U.S. Cl.
CPC ...
H10K 59/121 (2023.02); H10K 59/1201 (2023.02); H10K 59/122 (2023.02); H10K 59/131 (2023.02); H10K 71/233 (2023.02); H10K 71/60 (2023.02); H10K 71/621 (2023.02); H10K 59/80517 (2023.02);
Abstract

The present disclosure provides a display panel, a manufacturing method thereof, and a display apparatus. The display panel has a display region comprising a first display region and a second display region. A distribution density of pixel circuits in the first display region is smaller than that in the second display region. The display panel includes: a base substrate; a plurality of first pixel circuits disposed on a side of the base substrate and located in the second display region; traces disposed on a side of the first pixel circuits away from the base substrate; first light emitting devices disposed on a side of the traces away from the base substrate and located in the first display region, where first anodes in the first light emitting devices each include at least two conductive layers, and the at least two conductive layers include at least a first transparent electrode; connecting lines each disposed on a same layer as first transparent electrodes and electrically connected with a respective one of the first transparent electrodes, where the traces are used to electrically connect the respective first pixel circuits and the respective connecting lines, so that the first pixel circuits drive the first light emitting devices to emit light.

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