The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2026
Filed:
Mar. 25, 2021
Plessey Semiconductors Limited, Plymouth, GB;
Andrea Pinos, Plymouth, GB;
Wei Sin Tan, Plymouth, GB;
Jun Youn Kim, Plymouth, GB;
Xiang Yu, Plymouth, GB;
Simon Ashton, Plymouth, GB;
Samir Mezouari, Plymouth, GB;
Plessey Semiconductors Limited, Plymouth, GB;
Abstract
A method of manufacturing a LED precursor and a LED precursor is provided. The LED precursor is manufactured by forming a monolithic growth stack having a growth surface and forming a monolithic LED stack on the growth surface. The monolithic growth stack comprises a first semiconducting layer comprising a Group III-nitride, a second semiconducting layer, and third semiconducting layer. The second semiconducting layer comprises a first Group III-nitride including a donor dopant such that the second semiconducting layer has a donor density of at least 5×1018 cm-3. The second semiconducting layer has an areal porosity of at least 15% and a first in-plane lattice constant. The third semiconducting layer comprises a second Group III-nitride different to the first Group-III-nitride. The monolithic growth stack comprises a mesa structure comprising the third semiconducting layer such that the growth surface comprises a mesa surface of third semiconducting layer and a sidewall surface of the third semiconducting layer encircling the mesa surface. The sidewall surface of the third semiconducting layer is inclined relative to the mesa surface. The mesa surface of the third semiconducting layer has a second in-plane lattice constant which is greater than the first in-plane lattice constant.