The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Aug. 12, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Andreas Voerckel, Finkenstein, AT;

Hans Weber, Bayern, DE;

Tobias Franz Wolfgang Hoechbauer, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/832 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 62/8325 (2025.01); H01L 21/0465 (2013.01); H10D 12/031 (2025.01); H10D 30/668 (2025.01); H10D 62/127 (2025.01); H10D 64/513 (2025.01);
Abstract

A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.


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