The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2026
Filed:
Jul. 09, 2024
Applicant:
Socionext Inc., Kanagawa, JP;
Inventor:
Junji Iwahori, Yokohama, JP;
Assignee:
Socionext Inc., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/412 (2006.01); H10B 10/00 (2023.01); H10D 62/10 (2025.01); H10D 84/85 (2025.01); H10D 84/90 (2025.01); H10D 89/10 (2025.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); G11C 11/412 (2013.01); H10B 10/12 (2023.02); H10D 84/85 (2025.01); H10D 84/907 (2025.01); H10D 89/10 (2025.01); H10W 20/427 (2026.01); H10D 84/981 (2025.01);
Abstract
A layout structure of a capacitive cell using forksheet FETs is provided. In transistors Pand N, VDD is supplied to a pair of padsand a gate interconnect, and VSS is supplied to a pair of padsand a gate interconnect. Capacitances are produced between nanosheetsand the gate interconnectand between nanosheetsand the gate interconnect. The faces of the nanosheetscloser to the nanosheetsare exposed from the gate interconnect, and the faces of the nanosheetscloser to the nanosheetsare exposed from the gate interconnect