The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Dec. 05, 2022
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yuto Omizu, Tokyo, JP;

Yuya Abiko, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/00 (2025.01); H10P 30/20 (2026.01); H10P 32/10 (2026.01); H10P 32/14 (2026.01);
U.S. Cl.
CPC ...
H10D 30/668 (2025.01); H10D 30/0297 (2025.01); H10D 62/109 (2025.01); H10D 64/117 (2025.01); H10P 30/204 (2026.01); H10P 30/21 (2026.01); H10P 32/1406 (2026.01); H10P 32/171 (2026.01);
Abstract

Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity (Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.


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