The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Oct. 02, 2023
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Nobuyuki Fujimura, Yokkaichi, JP;

Tadashi Nakamura, Yokkaichi, JP;

Satoshi Shimizu, Yokkaichi, JP;

Takumi Moriyama, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 80/00 (2026.01); H10W 90/00 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 80/00 (2023.02); H10W 90/00 (2026.01); H10W 80/211 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/792 (2026.01);
Abstract

A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers, where the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench, memory openings vertically extending through a respective alternating stack of the pair of alternating stacks, memory opening fill structures located in a respective one of the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a lateral isolation trench fill structure located in the lateral isolation trench. Phosphorus-doped silicon oxide portions are located within or on sidewalls of the lateral isolation trench at levels of the insulating layers.


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