The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jan. 03, 2024
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Yijun Zhang, Shanghai, CN;

Bo Su, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10B 10/125 (2023.02); H10D 89/10 (2025.01);
Abstract

Semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate and a plurality of transistors located over the substrate. A transistor of the plurality of transistors includes: a channel layer parallel to a substrate surface, a gate structure surrounding the channel layer, and a source/drain doped region located on two sides of the gate structure. The source/drain doped region is in contact with the channel layer, and the gate structure is electrically isolated from the source/drain doped region. The semiconductor structure also includes a first metal structure located over the substrate, and a second metal structure located over the first metal structure and the gate structure. The first metal structure is in contact with the source/drain doped region. The first metal structure, the source/drain doped region and the gate structure are arranged along a first direction. The first direction is parallel to the substrate surface.


Find Patent Forward Citations

Zhang, Yijun. (2026). Semiconductor structure and method of forming semiconductor structure (U.S. Patent No. 12684752). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12684752

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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