Charge-steering-sampling phase discriminator, digital loop filter and charge-steering-sampling all digital phase-locked loop thereof

Abstract

The present invention discloses a CSS-PD (Charge-Steering-Sampling Phase Discriminator), a DLF (Digital Loop Filter) and a CSS-ADPLL (Charge-Steering-Sampling All Digital Phase-Locked Loop) thereof The CSS-PD includes a Frac-N C-DAC, a CSS, and a SAR-ADC. The CSS-PD has a controlling method including four steps: (1) charge presetting; (2) charge-steering sampling; (3) fractional charge compensating; (4) digitalizing. Wherein when ΔVsampled by the CSS included two errors ΔVand ΔV, ΔVhad fractional charge compensating by setting part of the capacitors of the Cof the Frac-N C-DAC to a V. Vwas satisfied the following formula: ΔV=D·C/(C+C)·V. Cis for capacitance of C, Cis also for capacitance of C, Cis also for capacitance of Cof the SAR-ADC, Dis the output signal of the Frac-N C-DAC. A CSS-ADPLL with the CSS-PD can obtain the performance of low jitter, low fractional division spurious and low reference spurious at the same time.