Flash memory reducing program rising time and program method thereof

Abstract

The present disclosure provides methods and apparatuses for reducing a program voltage rising time. In some embodiments, a flash memory includes a memory cell array including a plurality of memory cells, a target voltage generator configured to adjust a target voltage level of a word line recovery voltage provided to the plurality of memory cells, and a word line voltage controller configured to provide recovery control signals for controlling the target voltage level of the word line recovery voltage. The target voltage generator is further configured to adjust the word line recovery voltage provided to a selected word line to the target voltage level, based on the recovery control signals provided during a word line recovery operation following a program verify operation, and to reduce a program voltage rising time in a program execution operation period of a next program loop by adjusting the target voltage level.