Memory structure including three-dimensional nor memory strings and method of fabrication

Abstract

A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The storage transistors can be charge-trapping type storage transistors or ferroelectric storage transistors. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process. In some embodiments, the memory structure includes first and second semiconductor layers and respective first and second conductive layers forming the source and drain regions, which are spaced apart by a channel spacer dielectric layer. Each conductive layer is formed between the respective semiconductor layer and the channel spacer dielectric layer.