The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Sep. 27, 2022
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Isao Naritake, Kanagawa, JP;

Nobuyuki Ishikawa, Kanagawa, JP;

Yoshihiko Kinoshita, Kanagawa, JP;

Tetsuo Motomura, Kanagawa, JP;

Kazufumi Ikeda, Kanagawa, JP;

Tsukasa Ojiro, Kanagawa, JP;

Tomoko Shimada, Kanagawa, JP;

Kenichi Nagamatsu, Kanagawa, JP;

Koji Watanabe, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0038 (2013.01); G11C 13/0061 (2013.01); G11C 2013/0054 (2013.01);
Abstract

A semiconductor storage device includes one or more first memory cells connected in parallel between a first voltage supply line supplying a first voltage and a second voltage supply line supplying a second voltage different from the first voltage, and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line supplying the first voltage, wherein each of the first memory cells includes a first storage element having a resistance value corresponding to a first status or a second status, and a first cell transistor connected between the first storage element and the first voltage supply line, and each of the second memory cells includes a second storage element having a resistance value corresponding to a first status or a second status, and a second cell transistor connected between the second storage element and the third voltage supply line.


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