The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Dec. 12, 2023
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Nozomu Harada, Tokyo, JP;

Koji Sakui, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 5/06 (2006.01); G11C 11/4096 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 5/063 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H10B 12/20 (2023.02);
Abstract

A two-stage dynamic flash memory is formed as follows. An Nlayeris formed in a pillar-shaped semiconductor layer, which stands on an Nlayer, by performing a heat treatment, thereby producing an effect of forcing a donor impurity out into the pillar-shaped semiconductor layerfrom a silicide layer, which is a layer formed to surround a middle portion of the pillar-shaped semiconductor layerand contains the donor impurity. Gate oxide layerstoare formed on a side surface of the pillar-shaped semiconductor layer. Etching is performed with a single mask to form first to fourth gate conductor layers, andand a silicide layer, which have the same shape as viewed in plan view. An Nlayeris formed on a top portion of the pillar-shaped semiconductor layer


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