The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Oct. 10, 2025
Applicant:

Fuzhou University, Fuzhou, CN;

Inventors:

Chaoxing Wu, Fuzhou, CN;

Shuqian Zhang, Fuzhou, CN;

Yongai Zhang, Fuzhou, CN;

Xiongtu Zhou, Fuzhou, CN;

Yun Ye, Fuzhou, CN;

Tailiang Guo, Fuzhou, CN;

Assignee:

FUZHOU UNIVERSITY, Fuzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/32 (2016.01);
U.S. Cl.
CPC ...
G09G 3/2085 (2013.01); G09G 3/2074 (2013.01); G09G 3/32 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/0267 (2013.01); G09G 2320/064 (2013.01); G09G 2320/0666 (2013.01);
Abstract

The present invention discloses the CFI-ADA comprising: row scan lines, column scan lines, pixel regions corresponding to intersection areas of the respective row and column scan lines, and a frequency adjustable AC signal source. The pixel region is provided with row-column gating transistors and at least two CFI-LE Devices having different intrinsic driving frequencies. The row scan lines, column scan lines, and row-column gating transistors are configured to select corresponding pixel regions and apply the different frequency AC signal to the CFI-LE Devices. The CFI-LE Devices are activated at different operating frequencies according to their respective intrinsic driving frequencies when powered by the AC signal source. The present invention reduces the number of row and column scan lines under identical pixel conditions, thereby decreasing the area of the scanning circuitry and lowering the fabrication complexity of the display circuit.


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