The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Oct. 25, 2022
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

David H. Asher, Sutton, MA (US);

Catherine Choi, Hopkinton, MA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/20 (2020.01);
Abstract

A system and corresponding method perform verification. The system comprises a verification checker that monitors protocol messages of a coherency protocol. The coherency protocol is implemented via register-transfer level (RTL) logic of a chip to maintain cache coherency on the chip. The protocol messages are generated via the RTL logic. The system further comprises at least one memory. The verification checker performs verification of the coherency protocol based on system state stored in the at least one memory. The verification performed includes updating the system state based on the protocol messages monitored and controlling timing for the updating based on message classes. The message classes are associated with the protocol messages monitored. The verification checker reduces the likelihood that a processor design will have data inconsistency issues and can reduce time-to-market as verification implemented via the verification checker can make the verification effort more efficient.


Find Patent Forward Citations

Asher, David. (2026). System and method for coherency protocol verification (U.S. Patent No. 12682142). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12682142

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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