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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12682049 B1

PDFFull Text
Date of Patent:
Jul. 14, 2026

Filed:

Dec. 19, 2024

Method and system for insertion of cybersecurity and hardware assurance instruments within integrated circuits and electronic systems using multi-stage hardware marking

Applicant:

Amida Technology Solutions, Inc., Washington, DC (US);

Inventors:

Seema Naswa, Austin, TX (US);

Alfred Larry Crouch, Cedar Park, TX (US);

Peter Lawrence Levin, Silber Springs, MD (US);

Karpagam Karthikeyan, Glen Allen, VA (US);

Assignee:

Amida Technology Solutions, Inc., Washington, DC (US);

Attorneys:

Artie Pennington Law Offices, PLLC

Artie Pennington

Hannah Ward

Primary Examiner:

Philip J Chea

Assistant Examiner:

Jenise E Jackson

Int. Cl.
CPC ...
G06F 7/04 (2006.01); G06F 21/55 (2013.01);
U.S. Cl.
CPC ...
G06F 21/552 (2013.01); G06F 21/554 (2013.01); G06F 2221/034 (2013.01);
Abstract

A hardware trojan security system may perform a computer implemented method to secure an electronic facility in relation to a hardware trojan, by performing a trojan vulnerability analysis, locating an instrument site location, identifying a selected instrument in relation to an effect of the trojan, marking instrument control-side markers and instrument operative-side markers, marking facility model control-side markers and facility model operative-side markers, marking access architecture control-side markers, and connecting the instrument with the facility model and access architecture by matching corresponding markers.

Find Patent Forward Citations

Naswa, Seema. (2026). Method and system for insertion of cybersecurity and hardware assurance instruments within integrated circuits and electronic systems using multi-stage hardware marking (U.S. Patent No. 12682049). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12682049

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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