The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Sep. 10, 2024
Applicant:

Gigadevice Semiconductor Inc., Beijing, CN;

Inventors:

Sibo MA, Beijing, CN;

Hong Hu, Beijing, CN;

Yang Li, Beijing, CN;

Jianzhong Zhao, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/06 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0223 (2013.01); G11C 7/1069 (2013.01); G11C 7/222 (2013.01); G11C 8/06 (2013.01); G11C 8/08 (2013.01);
Abstract

Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified fixed-number-random-access mode, in which the memory array can be continuously read or written in response to receiving a fixed number of random access addresses; sequentially receiving the preset fixed number of access addresses via the data/address multiplexing line in succession; sequentially outputting data read in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates read operations, or sequentially receiving data to be written in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates write operations; and ending the mode by receiving an invalid chip enable signal.


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