The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jul. 22, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Ajit Kumar Agarwal, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01);
U.S. Cl.
CPC ...
G06F 9/52 (2013.01); G06F 9/544 (2013.01); G06F 9/545 (2013.01);
Abstract

Application code is compiled to generate code to be executed by the cores of a multi-core architecture. Generating the code includes mapping kernels of the application onto the DPEs, and generating main code for cores of the DPEs. The main code is generated by initializing locks for each kernel associated with the cores the DPEs. The locks are associated with input ports and output ports of the kernels. Further, buffers are initialized for the kernels. The buffers are associated with the locks and data streams. Subsequent to initializing the locks and initializing the buffers, the kernels are executed to generate data samples from the data streams. Subsequent to executing the kernels, the locks are released for subsequent calls of the kernels.


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