The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2026
Filed:
Sep. 12, 2023
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Hyung Jin Choi, Icheon-si, KR;
Chan Hui Jeong, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 11/4094 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0656 (2013.01); G06F 3/061 (2013.01); G06F 3/0679 (2013.01);
Abstract
A page buffer circuit of a memory device includes a sensing circuit configured to sense a voltage level of a sensing node changed according to a state of a bit line during a sensing operation. The page buffer circuit also includes a clamping circuit connected to the sensing node, wherein the claiming circuit is configured to control the voltage level of the sensing node not to drop below a clamping level in a predetermined period of the sensing operation.
Choi, Hyung. (2026). Page buffer circuit and peripheral circuit of a memory device (U.S. Patent No. 12681664). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12681664
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile