The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Dec. 13, 2024
Applicant:

Powerlattice Technologies Inc., Camas, WA (US);

Inventors:

Peng Zou, Camas, WA (US);

Gang Ren, Camas, WA (US);

Sujith S. Dermal, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/46 (2006.01); G06F 1/3215 (2019.01);
U.S. Cl.
CPC ...
G05F 1/468 (2013.01); G06F 1/3215 (2013.01);
Abstract

This application is directed to an electronic device having a configurable group of voltage regulator cells. The electronic device includes a group of voltage regulator cells operating based on parameter settings of individual voltage regulator cells, output a rail voltage, and provide the rail voltage to multiple power rails. The electronic device includes a memory component coupled to the group of voltage regulator cells. The memory component stores an encoding table including multiple register files, and a register file defines parameter settings for the individual voltage regulator cells of the group of voltage regulator cells. The electronic device includes a setting interface for receiving a parameter setting signal applied to select the register file among the multiple register files for defining the parameter settings for the group of voltage regulator cells. The electronic device includes a substrate where the group of voltage regulator cells and the setting interface are integrated.


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Zou, Peng. (2026). Power management techniques using location-mapped chiplet configuration (U.S. Patent No. 12681516). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12681516

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