The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Feb. 15, 2022
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Jong Su Kim, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeon8gi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); H10W 20/074 (2026.01); H10W 20/085 (2026.01); H10W 20/089 (2026.01); H10W 20/42 (2026.01); H10W 20/056 (2026.01);
Abstract

Various embodiments of the present disclosure improve integration degree of semiconductor devices by simultaneously forming interconnections extending in various directions through a single gap-fill process. The embodiments of the present invention provide an interconnection structure that is capable of simplifying semiconductor processing, a semiconductor device including the interconnection structure, and a method for fabricating the semiconductor device. According to an embodiment of the present disclosure, an interconnection structure comprises: a stack of a plurality of interconnections, wherein at least two layers of the plurality of interconnections extend in different directions, and a portion of a top surface of a lower interconnection of the at least two layers is in direct contact with a portion of a bottom surface of an upper interconnection of the at least two layers.


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