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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12677560 B1

PDFFull Text
Date of Patent:
Jul. 07, 2026

Filed:

Jul. 29, 2022

Display substrate and manufacturing method therefor, and display apparatus

Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Changchang Liu, Beijing, CN;

Xuewei Tian, Beijing, CN;

Ling Shi, Beijing, CN;

Liqiang Chen, Beijing, CN;

Assignees:

Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan, CN;

BOE Technology Group Co., Ltd., Beijing, CN;

Attorneys:

Ling Wu

Stephen Yang

Ling and Yang Intellectual Property

Primary Examiner:

Vongsavanh Sengdara

Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/80 (2023.01); H10K 59/88 (2023.01); H10K 77/10 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1315 (2023.02); H10K 59/1201 (2023.02); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/873 (2023.02); H10K 59/88 (2023.02); H10K 77/111 (2023.02);
Abstract

A display substrate, a manufacturing method therefor, and a display apparatus are disclosed. The display substrate includes a display area (), a bonding area () and a bezel area (). On a plane perpendicular to the display substrate, the display substrate includes a base substrate () and a driving circuit layer (). The substrate () at least includes a base conductive layer disposed between a first flexible layer (A) and a second flexible layer (C), the base conductive layer at least includes a first connection line (), the driving circuit layer () at least includes a data signal line () and a second connection line (), the second connection line () is connected to the first connection line () through a first lapping via (DV), the data signal line () is connected to the second connection line () through a second lapping via (DV).

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