The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Apr. 19, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Juseong Min, Suwon-si, KR;

Kyeonghoon Park, Suwon-si, KR;

Jae-Bok Baek, Suwon-si, KR;

Donghyuck Jang, Suwon-si, KR;

Jeehoon Han, Suwon-si, KR;

Taeyoon Hong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 10/00 (2026.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 62/116 (2025.01); H10D 64/513 (2025.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01);
Abstract

A semiconductor device include a substrate including a plurality of protrusions protruding from an upper surface thereof and arranged two-dimensionally in a first direction and a second direction intersecting each other, a first trench provided between the protrusions in the first direction, and a second trench provided between the protrusions in the second direction, a first device isolation layer filling the first trench, gate patterns disposed on the protrusions in the second direction, upper surfaces of the protrusions exposed at both sides of the gate patterns, respectively, and a second device isolation layer filling a space between the gate patterns in the second direction and the second trench, and each of the gate patterns has a first sidewall adjacent to the second trench and aligned with an inner wall of the second trench.


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