The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Apr. 29, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Dhanoop Varghese, Plano, TX (US);

Henry Litzmann Edwards, Garland, TX (US);

Pinghai Hao, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/65 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/65 (2025.01); H10D 30/0281 (2025.01); H10D 62/116 (2025.01); H10D 64/01 (2025.01); H10D 64/519 (2025.01);
Abstract

Semiconductor devices including selectively doped gate electrodes are described. The semiconductor device comprises a substrate including a body region and a drift region, a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region, and a field relief dielectric layer on the drift region, the field relief dielectric layer laterally abutting the gate dielectric layer at a location over the drift region. The semiconductor device also includes a gate electrode having an n-doped first portion, a p-doped second portion, and an n-doped third portion. The selectively doped second portion of the gate electrode is located over an intersection between the gate dielectric layer and the field relief dielectric layer.


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