Analog-to-digital converter and semiconductor device having the same

Abstract

The present disclosure relates to an analog-to-digital converter that minimizes or prevents a loss of charges charged in a capacitor array by controlling a switching sequence of switches when switching phases. The analog-to-digital converter includes a DAC circuit including a CDAC circuit and a RDAC circuit, a comparator that compares an output voltage of the DAC circuit with a common mode voltage and outputs a comparison result, and a control logic circuit that controls a switch operation of the DAC circuit and the comparison operation of the comparator in a sampling phase and a comparison phase, outputs digital data based on the comparison result of the comparator, and controls switches that apply the common mode voltage and first and second reference voltages to the capacitor array in the CDAC circuit in response to that the sampling phase is switched to the comparison phase based on a specific switching timing sequence.