The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Sep. 29, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Yogesh Darwhekar, Bangalore, IN;

Abhrarup Barman Roy, Bangalore, IN;

Subhashish Mukherjee, Bangalore, IN;

Peeyoosh Mirajkar, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/08 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 21/08 (2013.01); H03K 17/6871 (2013.01);
Abstract

In an example, a system includes an N divider coupled to an output of a low dropout regulator. The system also includes a load balancing circuit coupled to the N divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the N divider. The system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the N divider.


Find Patent Forward Citations

Darwhekar, Yogesh. (2026). Deterministic jitter compensation scheme for dtc timing path (U.S. Patent No. 12676617). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12676617

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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