The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Mar. 26, 2024
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Christopher Calvo, Plantation, FL (US);

Robert Gorday, Gainesville, FL (US);

Michael Wu, Austin, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/00 (2006.01); H03D 7/16 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03D 3/008 (2013.01); H03D 7/165 (2013.01); H03F 3/45973 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01);
Abstract

In one aspect, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal; a mixer coupled to the LNA to downconvert the RF signal to a second frequency signal; a quadrature transimpedance amplifier (TIA) to convert a current of the second frequency signal to a voltage signal, the quadrature TIA having an in-phase (I)-channel having an I-channel DC offset and a quadrature-phase (Q)-channel having a Q-channel DC offset; and a DC offset calibration circuit coupled to the quadrature TIA. The DC offset calibration circuit is configured to calibrate a DC offset of the quadrature TIA. The DC offset calibration circuit may be configured to independently determine an I-channel DC offset setting and independently determine a Q-channel DC offset setting, where the I-channel and Q-channels have a DC offset interdependency.


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