Memory device for controlling a data output order and an operating method thereof

Abstract

A memory device including: a memory cell array including pages each page including memory cells; a page buffer circuit including page buffers corresponding to the memory cells of each page, each of the page buffers including first through N-th latches; and a control logic to control first hard decision data and first soft decision data read in a first read operation on a first page to remain in a first page buffer during a second read operation on a second page, and control an output operation such that the first hard decision data is output after the first soft decision data is output when the memory device is set to a first output mode, wherein the first hard decision data is based on a normal read level and the first soft decision data is based on an offset read level read from the first page.