Memory device performing leakage detection operation

Abstract

In some embodiments, the memory device includes a memory cell array including a plurality of memory blocks including a plurality of word lines, a pass transistor circuit including a plurality of pass transistors coupled to the plurality of word lines, a row decoder configured to provide a block selection voltage to first terminals and a driving voltage to second terminals of the plurality of pass transistors, a voltage generator configured to generate the block selection voltage and the driving voltage, and a control circuit configured to control the row decoder and the voltage generator, perform a leakage detection operation on a target memory block of the plurality of memory blocks, set a plurality of first detection word lines of the target memory block to a first voltage level, and set a plurality of second detection word lines of the target memory block to a second voltage level.