The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Jul. 19, 2024
Applicant:

Fidelix Co., Ltd., Seongnam-si, KR;

Inventor:

Jae Jin Lee, Gwangju-si, KR;

Assignee:

FIDELIX CO., LTD., Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4094 (2006.01); G11C 11/4099 (2006.01); H03K 19/017 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 11/4099 (2013.01); H03K 19/01721 (2013.01); H03K 19/20 (2013.01);
Abstract

A bit line pre-charge voltage generating circuit in a semiconductor memory device may reduce current consumption. The bit line pre-charge voltage generating circuit includes a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage; a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage; a driving portion that includes a pull-up driving element and a pull-down driving element; and an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal The activation overlap reduction portion can minimize the overlap between the turn-on sections of the pull-up driving element and the pull-down driving element of the driving portion.


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