Memory core circuit having cell on periphery (cop) structure and memory device including the same

Abstract

A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits respectively disposed under the sub cell arrays. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. The wordlines extend in a row direction and are arranged in a column direction. The bitlines extend in the column direction and are arranged in the row direction. Each sub peripheral circuit is divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region.