The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2026
Filed:
Oct. 29, 2024
Faraday Technology Corp., Hsinchu, TW;
Sivaramakrishnan Subramanian, Bengaluru, IN;
Hussainvali Shaik, Bangalore, IN;
Sandeep Kumar Mohanta, Odisha, IN;
Pydi Siva Sekhar, Andhra Pradesh, IN;
Eswar Reddi, Andhrapradesh, IN;
Basimsetti Subrahmanyam Suresh, Andhra Pradesh, IN;
Faraday Technology Corp., Hsinchu, TW;
Abstract
A memory apparatus includes a memory device, a memory controller and a memory physical layer interface. The memory physical layer interface comprises a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit. The tap reset circuit generates a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset a DFE taps of the multi-tap DFE receiver during the gap interval between the read bursts. The tap reset circuit resets the plurality of DFE taps using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval. The tap reset circuit resets the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval. The second predetermined interval is greater than the first predetermined interval.