The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Mar. 30, 2022
Applicant:

Mediatek Inc., Hsinchu City, TW;

Inventors:

Kin-Hooi Dia, Hsinchu City, TW;

Ho-Chieh Hsieh, Hsinchu City, TW;

Assignee:

MEDIATEK INC., Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); H10D 84/856 (2025.01);
Abstract

Semiconductor structures are provided. A semiconductor structure includes a cell array. The cell array includes a first regular cell, a second regular cell and a first mixed cell. Each P-type transistor has a first threshold voltage and each N-type transistor has a second threshold voltage in the first regular cell. Each P-type transistor has a third threshold voltage and each N-type transistor has a fourth threshold voltage in the second regular cell. Each P-type transistor has the first threshold voltage and each N-type transistor has the fourth threshold voltage in the first mixed cell. The first regular cell, the second regular cell and the first mixed cell are arranged in the same row of the cell array. The first mixed cell is arranged between the first and second regular cells and is in contact with the first regular cell.


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