The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2026
Filed:
Jul. 26, 2024
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Eric Wayne Mahurin, Austin, TX (US);
Jinxia Bai, San Diego, CA (US);
Tejaswi Talluru, Roundrock, TX (US);
Hidayatullah Chowdary, Austin, TX (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 7/544 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
G06F 15/8046 (2013.01); G06F 7/5443 (2013.01); H03L 7/0818 (2013.01);
Abstract
The present disclosure is directed to an apparatus that includes a systolic array having an initial systolic stage that is clocked at a first edge of a clock signal. The apparatus further includes control logic configured to clock a first subset of a plurality of additional systolic stages of the systolic array at the first edge of the clock signal. The control logic is further configured to clock a second subset of the plurality of systolic stages at a second edge of the clock signal.