The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Dec. 11, 2024
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Wenjin Lu, Austin, TX (US);

David Frederick Greenberg, Austin, TX (US);

Premkishore Shivakumar, Austin, TX (US);

Daniel Frederick Stafford, Houston, TX (US);

Rohit Pandharinath Pawar, Austin, TX (US);

David Yue Williams, Austin, TX (US);

David Allen Brown, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01);
U.S. Cl.
CPC ...
G06F 13/20 (2013.01); G06F 2213/40 (2013.01);
Abstract

An interconnect circuit comprises an unblock-request-receiving interconnect circuit node configured to receive a given write push request specifying write target data and write target address information identifying one or more addressed locations to which the write target data is to be written, and to enforce a requirement that a conflicting read request, which requests a read to one of the one or more addressed locations identified by the write target address information specified by the given write push request, is blocked from completing until an unblocking condition is satisfied for the given write push request, where for at least one type of write push request, satisfaction of the unblocking condition is dependent on an unblock request for the given write push request being received by the unblock-request-receiving interconnect circuit node; and an unblock-request-transmitting interconnect circuit node configured to transmit the given write push request to the unblock-request-receiving interconnect circuit node, and to transmit the unblock request for the given write push request in response to receipt of a completion response for an older write push request transmitted by the unblock-request-transmitting interconnect circuit node.


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