The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2026
Filed:
Feb. 27, 2024
Sandisk Technologies, Inc., Milpitas, CA (US);
Julian Vlaiko, Kfar Saba, IL;
Dmitry Vaysman, San Jose, CA (US);
Roni Ankonina, Sunnyvale, CA (US);
Nissim Elmaleh, Meitar, IL;
Judah Gamliel Hahn, Ofra, IL;
Sandisk Technologies, Inc., Milpitas, CA (US);
Abstract
Instead of the Peripheral Component Interconnect (PCI) Express (PCIe) link speed modulation and the PCIe link power state being utilized separately, the PCIe link speed modulation and PCIe link power state strategies are used in combination. The combination balances between the PCIe front end energy cost, the backend energy cost, and the quality of service (QOS). The performance/power space of the solid state drive (SSD) is mapped to the PCIe link speed modulation and PCIe link power state strategies to configure four distinctive zones, which provide high QoS at high performance points with a graceful performance degradation towards the lower performance points. A power/thermal constrained system dictates a certain performance that the SSD will be able to satisfy optimally by using both methods at different performance points.