The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Feb. 23, 2024
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Mankit Lam, Colorado Springs, CO (US);

Julius Kovats, Manitou Springs, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 40/00 (2026.01); H10W 70/60 (2026.01); H10W 70/69 (2026.01); H10W 74/47 (2026.01); H10W 70/09 (2026.01); H10W 72/00 (2026.01); H10W 74/40 (2026.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 40/00 (2026.01); H10W 70/614 (2026.01); H10W 70/69 (2026.01); H10W 74/47 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 72/0198 (2026.01); H10W 72/07227 (2026.01); H10W 72/853 (2026.01); H10W 74/40 (2026.01); H10W 90/00 (2026.01); H10W 90/288 (2026.01);
Abstract

An integrated circuit (IC) device includes a die including a silicon region having a coefficient of thermal expansion (CTE), and a conductive contact on a first side of the first die. An encapsulant laterally adjacent the silicon region of the first die has a coefficient of thermal expansion (CTE), wherein a mismatch between the CTEand the CTEdefines a thermal stress interface between the silicon region and the encapsulant. The IC device includes a dielectric layer formed over the first die and the encapsulant, and includes a dielectric spacer region extending over and laterally across the thermal stress interface. The IC device includes a redistribution layer (RDL) including an RDL element formed over the dielectric spacer region and electrically connected to the conductive contact through an opening in the dielectric layer, wherein the RDL element is physically spaced apart from the thermal stress interface by the dielectric spacer region.


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