The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

May. 16, 2024
Applicant:

Pep Innovation Pte. Ltd., Singapore, SG;

Inventor:

Hwee Seng Chew, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/68 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H10P 72/00 (2026.01); H10P 72/50 (2026.01); H10P 72/70 (2026.01);
U.S. Cl.
CPC ...
H10P 72/53 (2026.01); H10P 72/0428 (2026.01); H10P 72/0606 (2026.01); H10P 72/0614 (2026.01); H10P 72/7402 (2026.01);
Abstract

The present application relates to methods for compensating for die shift during compression molding of semiconductor dies. The method includes using a compensated marked carrier which includes a plurality of physical carrier markings derived from original projected markings. These original projected markings are generated through projection of original virtual carrier markings, based on a green file, and are transformed by applying a compensation factor in a computing apparatus. The method includes steps of bonding semiconductor dies onto the compensated marked carrier using the physical carrier markings, and performing compression molding to encapsulate the semiconductor dies into a molded panel. Additionally, the disclosure encompasses methods for fabricating the compensated marked carrier and applying these methods in a panel-level semiconductor packaging process.


Find Patent Forward Citations

Loading…