Vertical type non-volatile memory devices and methods of fabricating the same

Abstract

According to some embodiments of inventive concepts, vertical nonvolatile memory devices and related methods may reduce chip size. The nonvolatile memory device may include a substrate that includes a cell array area and an extension area. A first gate structure layer on the substrate may include a plurality of first gate layers. A second gate structure layer on the first gate structure layer and on a contact separation layer may include a plurality of second gate layers. A plurality of first metal contacts may extend through the first gate structure layer and a plurality of second metal contacts may extend through the second gate structure layer. The contact separation layer may be between the first plurality of metal contacts and the second plurality of metal contacts, and each of the second metal contacts may be aligned with a respective one of the first metal contacts.