The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2026
Filed:
Dec. 16, 2024
Wenzhou University, Zhejiang, CN;
Gang Li, Zhejiang, CN;
Pengjun Wang, Zhejiang, CN;
Xilong Shao, Zhejiang, CN;
Junjie Zhou, Zhejiang, CN;
Bo Chen, Zhejiang, CN;
Wenzhou University, Zhejiang, CN;
Abstract
A strong PUF circuit with good stability and anti-ML attack capacity is provided. The strong PUF circuit includes n delay modules, n−1 interconnection modules, an arbiter array and an XOR gate, wherein n is an integer greater than or equal to 1, each delay module is implemented based on a bias source structure, and the number of transmission paths of input signals can be increased by means of the characteristics of the bias source structure of the delay module to realize a diversity of transmission, thus realizing a highly complex and unpredictable challenge-response mapping relation without multiple strong PUFs. The transmission characteristics (transmission paths) of the input signals can be further obfuscated by means of the interconnection modules. Only one XOR gate is used for generating response outputs to further improve the stability.