Digital quadrature clock for low jitter applications

Abstract

Presented are systems and methods for generating quadrature clock signals for high-speed signal processing and similar applications. In various embodiments, a first input signal is rotated by a first phase angle to obtain a first rotated signal that represents a first quadrature clock signal. A second input signal that is 180 degrees out-of-phase with the first signal is rotated by a second phase angle such as to produce a second rotated signal. The unaltered first input signal and the phase-shifted second signal are then combined to derive an interpolated signal. This interpolated signal may be used to generate a second quadrature clock signal. As a result, the presented systems and methods effectively addresses the challenges of low-jitter, high-accuracy clock signal generation in applications such as SERDES and other systems that require precise timing signals, thereby ensuring enhanced system performance, while reducing complexity and power consumption.