The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Sep. 05, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Naoaki Kokubun, Yokohama Kanagawa, JP;

Yuki Kondo, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
H03M 13/157 (2013.01);
Abstract

In an arithmetic circuit, a first substitution circuit calculates p/2 first evaluation values by using a first input polynomial having first-order to s-th-order coefficients of the error locator polynomial. When the number of errors is t/2 or less, the arithmetic circuit outputs p pieces of information including: error position information calculated from the first evaluation values obtained by substituting p/2 first check values, and error position information calculated from a second evaluation values obtained by substituting the first check values into a second input polynomial having coefficients obtained by converting coefficients of the first input polynomial. When the number of errors is larger than t/2, the arithmetic circuit outputs p/2 pieces of error position information based on the first evaluation values and third evaluation values obtained by converting the second evaluation values obtained by a third polynomial having (s+1)-th-order to t-th-order coefficients of the error locator polynomial.


Find Patent Forward Citations

Kokubun, Naoaki. (2026). Arithmetic circuit, memory system, and method of controlling nonvolatile memory (U.S. Patent No. 12671444). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12671444

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