The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Apr. 29, 2024
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventors:

Boyu Hu, Irvine, CA (US);

Guansheng Li, Irvine, CA (US);

Haitao Wang, Irvine, CA (US);

Chang Liu, Irvine, CA (US);

Heng Zhang, Irvine, CA (US);

Delong Cui, Tustin, CA (US);

Jun Cao, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/12 (2006.01); H03M 1/60 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1009 (2013.01); H03M 1/0624 (2013.01); H03M 1/1215 (2013.01); H03M 1/1255 (2013.01); H03M 1/60 (2013.01);
Abstract

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.


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