Noise mitigation in electronic devices including neural network circuits

Abstract

This disclosure is directed to noise mitigation for processing circuitry of an electronic device having a neural network circuit. A neural network circuit may include multiple neural network layers (e.g., a transformer) to perform inference operations. The processing circuitry may include a noise mitigation circuit to reduce a magnitude or magnitude response of noise signals, for example, at one or more frequencies. The noise mitigation circuit may reduce an amplitude of the noise signals by aperiodically providing different clock signals having different clock frequencies to the neural network layers during an inference operation. Alternatively or additionally, the noise mitigation circuit may reduce an amplitude of the noise signals by aperiodically changing clock signal frequencies and supply voltage values of the neural network layers during the inference operation.