Memory system, operating method of the memory system, and interface circuit of the memory system

Abstract

Provided is a memory system including a memory device including a plurality of non-volatile memories, each of the plurality of non-volatile memories being electrically connected to a buffer chip, and a memory controller electrically connected to the buffer chip and configured to transmit a reference clock signal used in correction of a data signal, wherein the buffer chip includes a delay clock generation chain configured to generate a first delay clock signal or a second delay clock signal from the reference clock signal, a first register configured to store the first delay clock signal, and a second register configured to store the second delay clock signal, and wherein the buffer chip is configured to perform compensation on a strobe signal of the data signal based on the first delay clock signal, and perform compensation on the data signal based on the second delay clock signal.