Ray cache with ray transform support for ray tracing

Abstract

Techniques are disclosed relating to caching data for ray tracing in graphics processors. In some embodiments, ray intersect accelerator circuitry includes traversal circuitry configured to perform intersection tests between rays and bounding regions of an acceleration data structure and transform circuitry configured to, in response to reaching a transform node in the acceleration data structure, transform first coordinates of a ray from a first coordinate space to generate second coordinates of the ray in a second coordinate space. Ray cache circuitry is configured to cache data that is accessible to the ray intersect accelerator circuitry, where an entry of the ray cache circuitry is configured to cache data for the ray that includes: the first coordinates of the ray in the first coordinate space, the second coordinates of the ray in the second coordinate space, and shared data for the ray that applies to both the first and second coordinates.